The present invention relates to a nonvolatile semiconductor memory device, a method of controlling the same, and a memory card or memory system using the same and, more particularly, to a nonvolatile semiconductor memory device in which memory cells each having a MOS transistor structure are connected to form a memory cell unit, a method of controlling the same, and a memory card or memory system using the same.
This application is based on Japanese Patent Application No. 08-345195, filed Dec. 25, 1996, the content of which is incorporated herein by reference.
Recently, as an electrically erasable nonvolatile semiconductor memory device, an EEPROM having a structure in which one unit is formed of memory cells and connected to a data line is known. In this structure, the number of contacts with data lines can be decreased in order to increase the integration degree. An example of the EEPROM has an arrangement in which memory cells are series-connected to form one unit cell (to be referred to as a NAND-type cell hereinafter). FIG. 1 is a plan view showing one NAND-type cell in an EEPROM of this type. FIGS. 2 and 3 are sectional views taken along the lines II--II and III--III in FIG. 1, respectively. The same reference numerals denote the same constituent elements, and a description thereof will be omitted.
As shown in FIGS. 1, 2, and 3, in the NAND-type cell, e.g., a p-type well 12 is formed on an n-type silicon substrate 14, and an element isolation insulating film 32 is selectively formed on the p-type well 12.
A NAND-type cell formed of memory cells (e.g., four memory cells) M11 to M14 and two selection transistors QS1 and QS2 which are series-connected to each other is formed in a region surrounded by the element isolation insulating film 32.
In a memory cell forming a NAND-type cell, a first gate insulating film 30 is formed on the p-type well 12 surrounded by the element isolation insulating film 32.
A floating gate 16 (16-1 to 16-4) made of, e.g., a polysilicon film is formed on the first gate insulating film 30. A second gate insulating film 34 is formed on the floating gate 16, and a control gate 18 (18-1 to 18-4) made of, e.g., a polysilicon film is formed on the second gate insulating film 34.
In the selection transistors QS1 and QS2, a gate insulating film is formed on the p-type well 12, and gate electrodes 20 and 22 made of polysilicon are formed on the gate insulating film. First layers 20a and 22a of the gate electrodes 20 and 22 are formed at the same time as the floating gate 16, and second layers 20b and 22b are formed at the same time as the control gate 18. In the gate electrodes 20 and 22, the first layers 20a and 22a and the second layers 20b and 22b are electrically connected at desired portions (not shown).
The control gates 18-1 to 18-4 of the memory cell are successively formed in the row direction, and connected to the control gates of the memory cells of an adjacent NAND-type cell to form word lines WL1 to WL4. The potentials of the word lines WL1 to WL4 are represented by Vcg1 to Vcg4. The gate electrodes 20 and 22 of the selection transistors QS1 and QS2 are also successively formed in the row direction, and serve as selection gate lines SG1 and SG2. The potentials of the selection gate lines SG1 and SG2 are represented by Vsg1 and Vsg2.
N-type diffusion layers 40, 42, 44, 46, 48, 50, and 52 serving as source and drain regions are formed on the p-type well 12. These source and drain regions are commonly used by adjacent memory cells, and adjacent memory cells and selection transistors. As a result, the current paths of the selection transistor QS1, the memory cells M11 to M14, and the selection transistor QS2 are series-connected to form a NAND-type cell. The drain region 40 of the selection transistor QS1 is connected to a bit line (BL1) 24 via an n.sup.+ -type diffusion layer 54 and a contact opening 26. The source region 52 of the selection transistor QS2 is connected to a source line.
FIG. 4 shows a so-called NAND-type EEPROM formed of integrating above-described NAND-type cells in an array.
A set of memory cells connected to the same word line is generally called one page. A set of pages between a selection transistor group on the drain side connected to a single selection gate line and a selection transistor group on the source side connected to a single selection gate line is called one NAND block or simply one block. One block is normally the minimum independent erasable unit.
For example, in FIG. 4, one page is formed of memory cells M11, M21, . . . , Mn1connected to the word line WL1. One block is formed of the memory cells M11, M12, . . . , Mn3, and Mn4 sandwiched between selection transistors QS1, QS3, . . . , QS2n-1 on the drain side and selection transistors QS2, QS4, . . . , QS2n on the source side. The drains of the selection transistors QS1, QS3, . . . , QS2n-1 are respectively connected to bit lines BL1, BL2, . . . , BLn, whereas the sources of the selection transistors QS2, QS4, . . . , QS2n receive a source potential Vs.
The operation of the NAND-type EEPROM shown in FIG. 4 will be described below.
FIG. 5 shows the voltage of the NAND-type cell, and FIG. 6 is a timing chart showing the operation of the NAND-type cell. An operation performed when data is written in a block formed of the memory cells M11 to Mn4 will be explained.
Before writing data in a memory cell, data already written in the memory cells are erased. Data is erased in units of NAND blocks. At this time, the contents of memory cells in the same NAND block are simultaneously erased. In a selected NAND block, the potentials Vcg1 to Vcg4 of all the word lines WL1 to WL4 are set to a reference potential VSS (e.g., 0V), and the high voltage VPP (e.g., 18V) is applied to a potential Vwell of the p-type well and a potential Vsub of the n-type substrate. Potentials Vbit1 , Vbit2, . . . of the bit lines BL1, BL2, . . . and potentials Vsg1 and Vsg2 of the selection gate lines SG1 and SG2 are set to the high voltage VPP, e.g., 18V. As a result, electrons are discharged from the floating gates to the substrate in all the memory cells to shift the threshold to the negative direction. This state is normally defined as a state "1". When data of the whole chip is to be erased, all NAND blocks are set in a selected state.
A data write operation will be described below.
Data is written in units of pages in the order from a memory cell most distant from the bit line. The high voltage VPP (e.g., 20V) is applied to a word line corresponding to a page subjected to a data-write operation in the NAND block, while an intermediate potential VM (e.g., 10V) is applied to the remaining non-selected word lines. Vsg1 is set to VM (10V), and Vsg2 is to VSS (0V). VSS or VM is applied to the bit lines BL1, BL2, . . . , BLn in accordance with write data. Upon applying VSS to the bit line (write "0"), the potential is transferred to a selected memory cell to inject electrons to its floating gate. As a result, the threshold of the selected memory cell shifts to the positive direction. Normally, this state is defined as a state "0". When VM is applied to the bit line (write "1"), the threshold does not change and remains negative because no electron is injected to the memory cell. This write operation is repeatedly performed in the order from the memory cells M14 to Mn4, M13 to Mn3, M12 to Mn2, and M11 to Mn1 of the respective pages.
A data read operation will be explained below. Data is read in units of cells. The potential of the control gate of a selected memory cell in a NAND block, e.g., the potential Vcg4 of the control gate of the memory cell M14 in FIG. 6 is set to VSS, and the potentials of the remaining control gates and the gate potentials of the selection transistors are set to VCC (e.g., 5V). At this time, whether a current flows in the selected memory cell M14 is checked to determine data.
An erroneous write mode generated in a data write will be described. The erroneous write mode is generated because the intermediate potential VM is applied to a non-selected word line in a write operation. Since VSS or VM is applied to the bit line in accordance with data, if the drain voltage is 0V (VSS) when the gate voltage of a non-selected memory cell is VM (about 10V), the memory cell becomes in a weak electron injection mode (weak write) in which a small number of electrons are injected to the floating gate. For example, in a 16-bit NAND-type cell obtained by series-connecting 16 memory cells, this erroneous write mode occurs 15 times in one write cycle (write to all pages in one block) in the worst case. Normally, however, even if the erroneous write mode occurs 15 times, this does not cause any write error (in this specification, erroneous write mode means a weak electron injection mode (weak write) in which a small number of electrons are injected to the floating gate, and write error means that a large number of electrons are injected to the floating gate so as to change the value of data) because a block is erased before a next write to the block to clear the data written weak.
As described above, in the EEPROM (so-called block erase/page write EEPROM) in which data is erased in units of blocks, no erroneous write mode poses any problem because only the influence of the erroneous write mode corresponding to the number of pages of one block at most is accumulated.
In recent years, however, the use of an EEPROM (so-called page erase/page write EEPROM) using not a block but a smaller page as the erase unit is examined. When data is erased in units of pages, the erroneous write mode poses a problem.
For example, the case wherein data is to be erased from a page connected to the word line WL2 and then data is to be written therein will be explained. Vcg2 is set to 0V, and a high voltage of 18V is applied to Vcg1, Vcg3, Vcg4, Vwell, and Vsub to perform a page erase. At this time, in only cells connected to the word line WL2, electric charges in the floating gates are discharged to the substrate. No discharge occurs in cells connected to the word lines WL1, WL3, and WL4. Then, data are written in the cells of the selected page. That is, a page write operation is performed. Vcg2 is set to 20V, Vcg1, Vcg3, and Vcg4 are to 10V, and write data are supplied to the bit lines BL1 to BLn to perform a write operation. At this time, cells connected to Vcg1, Vcg3, and Vcg4 become in the erroneous write mode.
In this manner, when data of only one page in a block is erased, and data is written in this page, the remaining memory cells in the same block are in the erroneous write mode during one cycle of the write time. For this reason, e.g., when a page erase/page write operation for the same page is repeatedly performed 10.sup.6 times, the remaining memory cells are in the erroneous write mode for a time 10.sup.6 times the write time. As for each of other pages in the same block, if a page erase/page write operation is performed 10.sup.6 times, when one block is formed of, e.g., 16 pages, the erroneous write mode state occurs 10.sup.6 .times.15 times in the worst case. In this case, a write error occurs, resulting in a failure.